1. Field of the Invention
The present invention relates to a semiconductor device in which bipolar transistors and FETs (field effect transistors) are merged to form basic cells.
2. Description of the Prior Art
FIG. 1 shows a conventional BiCMOS logic circuit having a totem-pole output buffer for compensating the low driving capacity of a CMOS circuit.
This arrangement involves a long output delay time, because MOS transistors to be used for the arrangement have been integrated in recent years, and therefore, the power source voltage of the MOS transistors is too low to increase the power source voltage dependency of the output delay time.
To deal with this problem, BiNMOS and BiRNMOS logic circuits each employing n-channel MOS transistors (hereinafter referred to as the NMOS transistors) instead of a bipolar transistor on the grounding side of an output stage of the circuit are frequently used for semiconductor integrated circuits fabricated according to a design rule of about 0.5 micrometers.
FIG. 2 shows a 2-input NAND gate as an example of the BiNMOS logic circuits, and FIG. 3 shows a 2-input NAND gate as an example of the BiRNMOS logic circuits. The BiRNMOS circuit of FIG. 3 has, in addition to the BiNMOS circuit of FIG. 2, NMOS transistors N1 and N2 for improving the speed of discharging the base charges of an NPN bipolar transistor B1 through a resistance R.
This BiNMOS or BiRNMOS circuit employs only one bipolar transistor B1 whose collector potential is always at a power source potential as shown in FIGS. 2 and 3.
When the BiNMOS circuit is used as an internal gate circuit of a gate array whose cells are identically arranged in a process before a wiring process, a collector region of the output NPN bipolar transistor B1 can be formed in an n-type well region where p-channel MOS transistors (hereinafter referred to as the PMOS transistors) P1 and P2 are formed.
An example of this kind of arrangement is disclosed in, for example, Japanese Laid-Open Patent No. 59-177945. This disclosure simply teaches arranging an output NPN bipolar transistor and PMOS transistors in the same n-type well region. This arrangement involves, therefore, an increased circuit area compared with a CMOS gate array that employs MOS transistors only. The disclosure, therefore, hardly realizes high integration of semiconductor devices.
FIG. 4 is a layout showing a basic cell of the CMOS gate array, and FIG. 5 is a layout showing a cell of a logic gate that has been designed to make full use of the layout of FIG. 4. In FIG. 5, an NPN bipolar transistor is disposed on the longitudinal side of the basic cell region. This layout increases a cell area approximately 25% more than that of FIG. 4.
FIGS. 6A and 6B are sectional and plan views showing another example of the conventional logic gates, in which an NPN bipolar transistor is merged in the source or drain region of a PMOS transistor of a basic cell of a CMOS gate array. In this arrangement, the base region of the NPN bipolar transistor and the source or drain region of the PMOS transistor will be formed in the same diffusion layer.
An impurity concentration of the base region of the bipolar transistor must be lower than that of the source of drain region of the PMOS transistor. If this low impurity concentration of the base region of the bipolar transistor is applied to form a p-type diffusion layer in which the source or drain region of the PMOS transistor is also to be formed, the arrangement of FIGS. 6A and 6B will deteriorate the properties of the PMOS transistor and thus those of the CMOS circuit.